1. Field of the Invention
This invention generally relates to the prediction of electrical test yield for semiconductor integrated circuits (IC), or of electronic packages, and the influence of design and process characteristics upon those tests; more particularly, to an efficient procedure for the prediction of random defect yields which are practical for large chips.
2. Description of the Related Art
Electrical test yield is the most variable productivity component from product to product, and through the evolution and development of a process technology. Electrical test yield, Y, is defined as the product of systematic (gross) yield, Y0, and random defect yield (usually the dominant component), YR. Defects may be randomly introduced during the various steps of IC fabrication. Some of these defects will cause electrical failures (faults), and similar electrical failures are collectively referred to as a failure mechanism. The random defect yield is a function of average number of faults per IC, or xcex9, which is the summation of the average faults for each of the failure mechanisms, i.e. xcex9=xcexa31 xcexi). The electrical test yield can therefore be mathematically defined as
Y=Y0xc2x7YR=Y0xc2x7(1+xcex9/xcex1)xe2x88x92xcex1,xe2x80x83xe2x80x83(Equation 1)
which is known as the negative binomial distribution. Other widely published yield models, such as Poisson, Seeds, Murphy, and Boltz-Einstein, may be used in place of the negative binomial distribution (Charles H. Stapper, et al.,xe2x80x9cIntegrated Circuit Yield Statisticsxe2x80x9d, Proceedings of the IEEE, Vol. 71, Number 4, April, 1983, incorporated herein by reference), however, the mathematics defining the average faults for a particular IC remains the same. Alternatively, some IC manufacturers compute the average faults as the product of the chip area with the average fault density; however, the fault density must be empirically determined, and varies because of diverse IC functional content.
For a given failure mechanism, numbered i, the average number of faults, xcexi, is defined as the product of the critical area, ACi, which is dependent upon physical layout and the defect density, DDi. In Equation 2, critical area is shown as the product of the average probability of failure, xcex8i, or percent critical area, and the area of the chip, A.
xcexi=ACixc2x7DDi=(xcex8ixc2x7A)xc2x7DDixe2x80x83xe2x80x83(Equation 2)
Critical area has been defined as the area in which the center of a defect must fall to cause an electrical failure in an integrated circuit (Stapper, et al, supra, and Wojciech Maly, et al, xe2x80x9cYield Estimation Model for VLSI Artwork Evaluationxe2x80x9d, Electronics Letters, Vol. 19, Number 6, March, 1983, incorporated herein by reference). Thus, a key distinction exists between defects and faults. While all faults are presumed to be caused by defects, not all defects cause faults. In this invention, defect size will be characterized by the radius of the defect, denoted r. The average probability of failure is defined as an infinite integral (which is an integral from a minimum defect radius, r0, to an infinite radius, ∞) over the defect radii:
xe2x80x83xcex8i=∫Pi(r)xc2x7S(r)drxe2x80x83xe2x80x83(Equation 3)
where Pi(r) is the probability of failure function for a given failure mechanism, and is a function of defect radius, and S(r) is the size distribution, which is also a function of defect radius. While any size distribution function may be used, frequently fabricator defect inspection data is fit to equation 4:
S(r)=SK/rxcex2xe2x80x83xe2x80x83(Equation 4)
The inventive methods described herein center around the computation of the probability of failure function for a given failure mechanism, Pi(r). This function depends on the detail design of the IC, which is generally described in the form of a database of 2D geometries or shapes. The formal definition of the probability of failure function is:
Pi(r)=∫X∫Yxcex4i(x,y,r)dy dyxe2x80x83xe2x80x83(Equation 5)
where the values of the function xcex4i(x,y,r) is a 1 if a defect of radius r at location (x,y) causes a fault, and 0 otherwise.
Other approaches to model electrical test yield depend upon design shape algorithms calculating probability of failures by failure mechanism for a particular IC, (Sean Fitzpatrick, et al, xe2x80x9cA Comparison of Critical Area Analysis Toolsxe2x80x9d, IEEE/SEMI Advanced Semiconductor Manufacturing Conference Proceedings, September, 1998, and Gerard A. Allen, xe2x80x9cA Comparison of Efficient Dot Throwing and Shape Shifting Extra Material Critical Area Estimationxe2x80x9d, IEEE Defect and Fault Tolerance in VLSI System Proceedings, December, 1998, each incorporated herein by reference). One approach is the widely published Monte Carlo technique which simulates defects of predetermined sizes randomly falling on the design. Geometric (shape shifting) techniques allow a direct computation of a probability of failure for a given defect size. This method may be combined with sampling small portions of the design to ease the enormous compute resource requirements. All of these approaches are targeted at the specific problem of calculating the probability of failure for a predetermined defect size. Since it is not practical to calculate a probability of failure for every possible defect size, the defect size distribution must be approximated, introducing error into the larger problem of projecting electrical test yield. Consequently, all of the yield estimation techniques require the analyst to make some assumptions, either about the physical design characteristics, the defect size distribution, or the distribution of defects across failure mechanisms and process levels. The result is a yield estimate in which the error is not clearly understood, and there was likely an excessive amount of computer resource spent on the problem. For a fabricator making multiple ICs, the problem quickly becomes self-limiting. This application details a procedure that allows for optimization of the computer resources required for the calculation of the probability of failure for a particular failure mechanism at a specific defect size. This optimization is based upon an integrated approach, with complete error management and computational time controls, for projecting electrical test yield of a particular IC. Moreover, this procedure is practical for a manufacturing environment where multiple ICs of complex function are fabricated.
It is, therefore, an object of the present invention to provide a structure and method for computing the electrical test yield of an IC. The present invention takes as input an IC in the form of a database of shapes, and a fabrication process described in terms of failure mechanisms, defect densities per failure mechanism, defect size distribution, and a yield model. The present invention computes an estimate of the electrical test yield, including the average number of faults per IC, the average number of faults per failure mechanism of the IC, and an estimate of the error in the computation of these quantities.
The present invention computes a predicted yield of an IC that will be manufactured with a given manufacturing technology through the following processes:
1. Subdivide the IC into subdivisions, each of which contains multiple layers, each layer relating to a different failure mechanism. These subdivisions are called failure mechanism subdivisions.
2. Optionally, partition the failure mechanism subdivisions by area. The objective of these two partitioning steps is to reduce the computational effort of the remaining steps.
3. Pre-process the shapes in each partition to apply manufacturing process simulation steps such as layer biasing (shrinks or expands), optical proximity effects, etc.
4. Compute an initial estimate of the average number of faults for each failure mechanism (e.g., short, open, etc.) and each area partition by numerical integration of the percent critical area (e.g., numerical integration of a failure mechanism""s average probability of failure). This initial integration will produce a list of defect sizes for each failure mechanism (and each partition of each failure mechanism). The computational effort of this step is controlled by a maximum integration error limit, a sample size for the population of defects of each defect size (radius), and a maximum number of allowable faults.
5. Compute the final estimate of the average number of faults per IC by iteratively reducing the statistical error of the computation resulting from step 4 by repeating steps 6-10 until the statistical error is below the desired error limit.
6. Select the total number of defects (or total sample size) to be analyzed.
7. Distribute the total sample size among all the defect sizes of all the failure mechanisms. The sample sizes for each defect size of each defect mechanism are selected to maximize the reduction in the statistical error.
8. Compute probability of fault for each defect size and each defect mechanism with the selected sample size.
9. Compute the average number of faults for the current samples and the statistical error of the current sample.
10. Combine the results of this sample with the results of previous samples.
11. Compute the yield estimate using equation 1 or a similar equation.
It is a further object of the present invention to compute the average number of faults for a failure mechanism by predicting defect sizes and the number of defects by defect size (sample size), selecting a location and size for each defect, computing whether each defect results in a fault, summing the number of faults to compute the probability of failure by defect size, thus producing a probability of failure function, and integrating the product of the probability of failure function with the defect size distribution function to obtain the average number of faults as shown in Equation 2.
This invention controls the error in the integration that computes the average number of faults by a controlled selection of the number of defect sizes and of the specific defect sizes.
This invention also controls the statistical error of the average number of faults per IC by a controlled selection of the number of defects per defect size for each failure mechanism. The controlled selection of sample sizes takes into account the relative importance of the individual statistical errors of each defect size of each failure mechanism in the total statistical error of the average number of faults per IC.
The invention may also include partitioning the IC, computing the average number of faults per failure mechanism for each partition, and combining the average number of faults for all partitions and all the failure mechanisms to produce the average faults for the IC. The method for the control of the statistical error is extended to include partitioning of the IC.
The invention may also comprise a system for computing the electrical test yield of an IC that includes a computational unit which determines whether a defect causes a fault on the IC, another computational unit for computing a probability of failure for each defect size of each failure mechanism, and a further computational unit that selects defect sizes for a failure mechanism, computes the average number of faults for each failure mechanism, and then selects the sample sizes for each defect size.
The inventive system may also include a plurality of computational units simultaneously computing the average number of faults for each failure mechanism in each partition of the IC. The inventive system may further include a plurality of the computational units simultaneously computing a probability of failure for each of the defects and/or a sample size selector controlling statistical error of the probability of failure for the IC by controlled selection of a sample size of the defects in the predicting step. The sample size selector can also control integration error of the probability of failure for the IC by controlled selection of sizes of the defects and controlled selection of a number of the sizes.